Dynamic circuits are not robust under noisy condition. For example, a typical dynamic domino circuit uses a half or full latch to hold its dynamic nodes. However, under noisy conditions, these nodes can couple to noise and lose their data. Thus, a need exists for a dynamic domino circuit that is robust under noisy condition.
As another example, in many kinds of dynamic adders, inversion of carry that is required at the end of the carry chain is either accomplished by using a static inverter (extra gate delay) followed by static circuits, or having a separate chain of logic to generate carry bar (area penalty). For a really fast implementation, four chains of logic (g, ˜g, p, ˜p) are needed, thereby consuming a lot of area. Thus, a need exists for a dynamic adder that does not use a static inverter that causes extra gate delay A further need exists for a dynamic adder that does not consume a lot of area.
Furthermore, in most dynamic adders, a latch is required at the output to preserve the generated sum during circuit precharge. A need exists to improve the speed of the adders by cutting the latch delay while not requiring complex clocking.